Three-dimensional (3D) integrated circuit devices are experiencing extremely active development in the industry. One problem experienced in the fabrication of 3D integrated circuit devices is that general purpose substrate thinning techniques do not allow the final substrate to be produced with a controlled thickness that is thin enough to allow high-density through-silicon vias with reasonable aspect ratios to be realized. One known technique for overcoming this problem is utilizing a buried oxide layer (BOX) as the etch stop. However, this technique only works for silicon-on-insulator (SOI) wafers. Further, even with an SOI wafer, this technique does not work for SOI circuits having structures that extend below the buried oxide, such as an embedded DRAM (e-DRAM) trench.
Another known technique for overcoming this problem is utilizing a double buried oxide layer (double-BOX) structure. However, this technique greatly increases the manufacturing cost. Further, like the single buried oxide layer structure solution, the double-BOX technique requires protection of the substrate from the other wafer. Such protection is required because, while the SOI wafer acts as an etch stop, it does not provide selectivity between the different substrates.
Yet another known technique for overcoming this problem is to not use an etch stop but to perform “blind” thinning. However, this technique does not allow the wafers to be thinned aggressively and creates uniformity problems. Further, for integrated circuits that require a high density of 3D vias, this technique also forces the use of high aspect ratio vias that cannot be filled with copper. Instead, tungsten has to be used for the vias, which has three times higher resistivity than copper.
Another problem experienced in the fabrication of 3D integrated circuit devices is that stacking three or more layers to create a multi-layer stack leads to yield loss. One technique that attempts to overcome this problem is to stack layers through bonding to temporary handle wafers. However, the use of such a temporary handle wafer (e.g., a glass wafer) induces overlay distortions that degrade the alignment overlay between the wafers. That is, this technique does not allow high-precision optical alignment in subsequent lithographic steps. Without high-precision optical alignment, the via density is degraded and large capture pads with high parasitic capacitances must be used. Further, the use of such bonding to temporary handle wafers does allow flexibility in the way the wafers are stacked.
Another technique that attempts to overcome this problem is to simply use a direct face-to-face joining of the wafers. However, such direct face-to-face joining is problematic because the bottom wafer (which usually is a logic wafer) must then be used as the handle wafer throughout the stacking process. While this may be acceptable in the fabrication of a two layer stack, for a multi-layer (i.e., three or more layer) stack this means that the logic wafer must go through many bonding and thinning steps. This increases the probability of catastrophic failure and loss of the entire integrated circuit, including the logic wafer that is often the most expensive wafer in the stack.